Design and development of a custom RISC-V pipeline for two-way ranging (TWR) with ultra-wideband (UWB) technology (in collaboration with Prof. Luca Mottola, Politecnico di Milano, Italy)

Goal of the thesis is to prototype a custom RISC-V pipeline to support two-way ranging (TWR) with ultra-wideband (UWB) technology. TWR is a distance measurement method that uses the round-trip time of a UWB signal exchanged between two devices to calculate the precise distance between them. TWR technology is used in mobile computing and robotics to implement location-aware functionality and robot coordination. Distance values are obtained from low-level features of UWB signals by applying a specific processing pipeline, which may be optimized with a dedicated RISC-V design.


Exploring Security Vulnerabilities in the OpenTitan Framework: A Comprehensive Analysis and Testing Approach

This work focuses on an in-depth security evaluation of the OpenTitan framework which is an open-source silicon root of trust designed to reinforce trusted computing on hardware-level systems. The research will begin with a thorough review of OpenTitan’s architecture, security features, and implementation details to identify potential weakness points. Building on this understanding, the project will employ systematic testing methods, including static code analysis, fuzzing, and hardware penetration testing, to uncover vulnerabilities and assess the impact of any discovered flaws on system integrity.


Development of a Multi-Core RISC-V SoC for Harsh Environments (in collaboration with Dr. Luigi Dilillo, University of Montpellier, France)

Radiation-induced effects, such as Single Event Upsets (SEU) and Total Ionizing Dose (TID), pose significant challenges for electronic systems operating in space and other harsh environments. This internship will focus on extending an existing RISC-V-based System-on-Chip to a multi-core architecture in order to enhance performance and fault tolerance against radiation effects. The work involves modifying the existing VHDL design to support multiple cores, implementing inter-core communication and synchronization, and integrating fault-mitigation techniques. Candidates should have experience in VHDL, processor architecture, C programming, and microcontrollers.


Exploiting GPU Microarchitectures for Novel Hardware Attacks: Investigating Memory Leaks and Arbitrary Code Execution Without Physical Access

This thesis will investigate how modern Graphics Processing Units (GPUs) can be exploited to reveal sensitive data or run unauthorized code, all without requiring physical access or elevated permissions. By studying GPU-specific features, such as caching techniques, memory management, and parallel processing pipelines, the project aims to uncover new attack vectors and demonstrate them through proof-of-concept exploits. Finally, the research will suggest countermeasures and improved design strategies to enhance GPU security against these emerging threats.


Design of Integrated GPU Architectures for RISC-V System-on-Chip (SoC) Platforms

This thesis explores the development of new integrated GPU architectures within RISC-V SoC platforms. By designing GPU modules that are seamlessly integrated with the RISC-V architecture, the research will focus on improving graphical processing efficiency and enabling more powerful and energy-efficient SoC solutions for diverse applications.


Development of Novel Trusted Execution Environments (TEEs)

This thesis focuses on the design and development of new Trusted Execution Environments (TEEs) to enhance the security of computing systems. The research will explore innovative TEE architectures that provide improved protection for sensitive data and operations, particularly in embedded systems, ensuring that security is maintained even in the presence of malicious attacks (Transient Execution Attacks like Spectre and Meltdown, for example) or software vulnerabilities.


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