My publications can be classified as:
- 25 papers in refereed international journals
- 1 chapter in international research books
- 1 keynote talk
- 1 tutorial
- 44 papers in refereed international conferences, symposia and workshops, and
- 9 other talks and poster presentations
- 7 invited talks and seminars
Num. of citations: 644, h-index 14 (source Google Scholar, October 2024)
Num. of citations: 428, h-index 11 (source Scopus, October 2024)
Above the complete list of my publications (the authors of the papers marked with * are listed in alphabetical order).
Papers related to fault tolerance, test and diagnosis are marked in green, while papers related to security are marked in blue.
Journals
2024
Resilience of Deep Learning applications: a systematic literature review of analysis and hardening techniques
Cristiana Bolchini, Luca Cassano, Antonio Miele
In Computer Science Review, Volume 54, November 2024 (*)
2023
Fast and Accurate Error Simulation for CNNs against Soft Errors
Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Toschi
In IEEE Transactions on Computers, vol. 72, no. 4, pp. 984-997, 1 April 2023 (*)
Optimizing the Use of Behavioral Locking for High-Level Synthesis
Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri
In IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems, vol. 42, no. 2, pp. 462-472, Feb. 2023
2022
DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN
Luca Cassano, Mattia Iamundo, Tomas Antonio Lopez, Alessandro Nazzari, Giorgio Di Natale
In Journal of Systems Architecture, vol. 129, 2022
Is Your FPGA Bitstream Hardware Trojan-free? Machine Learning Can Provide an Answer
Alessandro Palumbo, Luca Cassano, Bruno Luzzi, José Alberto Hernández, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi
In Journal of Systems Architecture, vol. 128, 2022
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
Kerem Arıkan, Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Salvatore Pontarelli, Giuseppe Bianchi, Oguz Ergin, Marco Ottavi
In IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 7, pp. 938-951, July 2022
Approximation-based Fault Tolerance in Image Processing Applications
Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele
In IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 2, pp. 648-661, 1 April-June 2022 (*)
Design of Fault Tolerant Distributed Cyber-Physical Systems for Smart Environments
Luca Cassano, Antonio Miele, Francesco Mione, Nicola Tonellotto, Carlo Vallati
In IEEE Embedded Systems Letters, vol. 14, no. 2, pp. 79-82, June 2022 (*)
A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures
Antonio Miele, Henry Zàrate, Luca Cassano, Cristiana Bolchini, Jorge Ortiz
In ACM Transactions on Internet of Things Volume 3, issue 3, August 2022, Article No. 17, pp 1–29
Fault Impact Estimation for Lightweight Fault Detection in Image Filtering
Cristiana Bolchini, Giacomo Boracchi, Luca Cassano, Antonio Miele, Diego Stucchi
In IEEE Transactions on Computers vol. 71, no. 2, pp. 282-295, 1 Feb. 2022 (*)
2021
Securing RSA Hardware Accelerators through Residue Checking
Ana Lasheras, Ramon Canal, Eva Rodríguez and Luca Cassano
In Microelectronics Reliability Volume 116, 2021
2020
A Methodology for the Design and Deployment of Distributed Cyber-Physical Systems for Smart Environments
Giacomo Tanganelli, Luca Cassano, Antonio Miele, Carlo Vallati
In Future Generation Computer Systems Volume 109, August 2020, Pages 420-430
A Neural Network Based Fault Management Scheme for Reliable Image Processing
Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Erdem Koyuncu, Antonio Miele
In IEEE Transactions on Computers Volume: 69 , Issue: 5 , May 1 2020 , pp 764 - 776 (*)
2018
OLT(RE)2: an On-Line on-demand Testing approach for permanent Radiation Effects in REcongurable systems
D. Cozzi, S. Korf, L. Cassano, J. Hagemeyer, A. Domenici, C. Bernardeschi, M. Porrmann and L.Sterpone
In IEEE Transactions on Emerging Topics in Computing vol. 6, num 4 (2018), pp 511-523
2017
A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis
C. Bolchini and L. Cassano
In IEEE Design & Test vol. 34, n. 2 (2017), pp. 79-86
(*)
2016
UA2TPG: An untestability analyzer and testpattern generator for SEUs in the configuration memory of SRAM-based FPGAs
C. Bernardeschi, L. Cassano, A. Domenici and L. Sterpone
In Integration, the VLSI Journal vol. 55 (2016), pp. 85-97
(*)
A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards
Cristiana Bolchini and Luca Cassano
In IEEE Transactions on Computers vol. 65, no. 1, (2016), pp. 42-52
(*)
Adapting the duty cycle to traffic load in a preamble sampling MAC for WSNs
M. Avvenuti, C. Bernardeschi, L. Cassano, and A. Vecchio
In Ad Hoc & Sensor Wireless Networks vol. 31, no. 1-4, (2016), pp. 101-129 (*)
2015
SRAM-based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies
C. Bernardeschi, L. Cassano, and A. Domenici
In Journal of Computer Science and Technology
vol.30, issue 2, pages 373-390, Mar. 2015, DOI 10.1007/s11390-015-1530-5 (*)
An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards
Cristiana Bolchini, Luca Cassano, Paolo Garza, Elisa Quintarelli, and Fabio Salice
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 5, pp. 835-848, May 2015 (*)
2014
AENEAS: an Energy-Aware Simulator of Automatic Weather Stations
D. Cesarini, L. Cassano, M. Avvenuti, M. Kuri, V. Bilas
In IEEE Sensors Journal
vol.14, no.11, pp.3932-3943, Nov. 2014, DOI: 10.1109/JSEN.2014.2353011
ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-based FPGAs
C. Bernardeschi, L. Cassano, A. Domenici, and L. Sterpone
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume: 33, Issue: 9, Pages: 1342-1355, Sept. 2014, DOI: 10.1109/TCAD.2014.2329419 (*)
Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-ion Batteries
F. Baronti, C. Bernardeschi, L. Cassano, A. Domenici, R. Roncella, R. Saletti
In IEEE Transactions on Industrial Informatics
vol.10, no.2, pp.1003-1011, May 2014, DOI: 10.1109/TII.2014.2299236 (*)
2013
GABES: a Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs
C. Bernardeschi, L. Cassano, M.G.C.A. Cimino, A. Domenici
In Journal of Systems Architecture
vol. 59, issue 10, part D, November 2013, pag. 1243-1254, ISSN: 1383-7621, DOI: 10.1016/j.sysarc.2013.10.006 (*)
2011
Simulation and Test-Case Generation for PVS Specifications of Control Logics
C. Bernardeschi, L. Cassano, A. Domenici, P. Masci
In International Journal On Advances in Software
vol. 5, nr. 1&2, ISSN: 1942-2628 (*)
Book Chapters
2015
On the use of Stochastic Activity Networks for an Energy-aware Simulation of Automatic Weather Stations
Luca Cassano, Daniel Cesarini, Marco Avvenuti
In Handbook of Research on Computational Simulation and Modeling in Engineering
Keynote talks
2022
Advances in dependable image processing and deep learning
Luca Cassano
In PESW 2022, The 10th Prague Embedded Systems Workshop
Tutorials
2016
Board-level functional fault diagnosis: industry needs and research solutions
Luca Cassano, Krishnendu Chakrabarty and Bill Eklow
In DATE 2016, Design Automation & Test in Europe
Conferences
2024
An experimental comparison of RISC-V processors: performance, power, area and security
Elia Lazzeri, Bruno Endres Forlin, Gianluca Furano, Marco Ottavi, Luca Cassano
Accepted at DFTS 2024, the 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 8th - 10th, 2024, Harwell campus in Oxfordshire, UK
Range restriction to harden CNNs against hardware faults: a broad empirical analysis
(Winner of the best paper award)
Cristiana Bolchini, Luca Cassano, Antonio Miele, Dario Passarello
Accepted at DFTS 2024, the 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 8th - 10th, 2024, Harwell campus in Oxfordshire, UK (*)
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space (Winner of the outstanding student presentation award)
Alessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini
In ETS 2024, the 29th IEEE European Test Symposium, May 20-24 in The Hague, Netherlands
Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes
Bruno Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano and Marco Ottavi
In DATE 2024, the Design, Automation and Test in Europe Conference, 25th - 27th March 2024, Valencia, Spain
2023
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications
Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari and Dario Passarello
In DFTS 2023, the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 3rd - 5th, 2023, Juan-Les-Pins, France (*)
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes
Alessandro Palumbo, Luca Cassano, Pedro Reviriego and Marco Ottavi
In DFTS 2023, the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 3rd - 5th, 2023, Juan-Les-Pins, France
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
Alessandro Palumbo, Marco Ottavi and Luca Cassano
In DFTS 2023, the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 3rd - 5th, 2023, Juan-Les-Pins, France
Towards dependable RISC-V cores for edge computing devices
Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola
In IOLTS 2023, the 29th IEEE International Symposium on On-Line Testing and Robust System Design, July 3rd - 5th, 2023 Chania (Crete), Greece
2022
Is RISC-V ready for Space? A Security Perspective
Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi
In DFTS 2022, 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 19th - 21st, 2022, Austin, Texas (USA)
Selective Hardening of CNNs based on Layer Vulnerability Estimation
Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari
In DFTS 2022, 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 19th - 21st, 2022, Austin, Texas (USA) (*)
On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors
Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale
In DDECS 2022, the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Prague, Czech Republic, April 6 – 8, 2022
Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?
Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Ioana Vatajelu
In DDECS 2022, the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Prague, Czech Republic, April 6 – 8, 2022 (*)
2021
Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications
Cristiana Bolchini, Luca Cassano, Atonio Miele, Andrea Mazzeo
In DFTS 2021, the 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Online Event, October 6 – 8, 2021 (*)
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses
Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Giuseppe Bianchi and Marco Ottavi
In DFTS 2021, the 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Online Event, October 6 – 8, 2021
2020
Lightweight Fault Detection and Management for Image Restoration
Cristiana Bolchini, Luca Cassano, Atonio Miele, Matteo Biasielli
In DFTS 2020, the 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, ESA-ESRIN, Frascati (Rome) Italy, October 19 – October 21, 2020 (*)
Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis
Ana Lasheras, Ramon Canal, Eva Rodríguez and Luca Cassano
In IOLTS 2020, the 26th IEEE International Symposium on On-Line Testing and Robust System Design, Naples (Italy), July 13-15, 2020
Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs
Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele
In IOLTS 2020, the 26th IEEE International Symposium on On-Line Testing and Robust System Design, Naples (Italy), July 13-15, 2020 (*)
A Microprocessor Protection Architecture against Hardware Trojans in Memories
Alperen Bolat, Luca Cassano, Pedro Reviriego, Oguz Ergin, Marco Ottavi
In DTIS 2020, the IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Marrakesh, Morocco, April 1-33, 2020, pp. 1 - 6
An Approximation-based Fault Detection Scheme for Image Processing Applications
Matteo Biasielli, Luca Cassano, Atonio Miele
In DATE 2020, Design Automation & Test in Europe, Grenoble, France, March 9-13, 2020, pp. 1 - 4 (*)
2019
Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking
Ana Lasheras, Ramon Canal, Eva Rodríguez and Luca Cassano
In DFTS 2019 the 32th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 2 – October 4, 2019, ESA-ESTEC & TU Delft, Netherlands
HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems
Cristiana Bolchini, Luca Cassano, Ivan Montalbano, Giampiero Repole, Andrea Zanetti, Giorgio Di Natale
In IOLTS 2019 the 25th IEEE International Symposium on On-Line Testing and Robust System Design, Rhodes Island, Greece, July 1-3, 2019 (*)
A Smart Fault Detection Scheme for Reliable Image Processing Applications
Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Atonio Miele
In DATE 2019, Design Automation & Test in Europe, Florence, Italy, March 14-18, 2019, pp. 1 - 6 (*)
2016
Lifetime-aware Load Distribution Policies in Multi-core Systems: An In-depth Analysis
Cristiana Bolchini, Luca Cassano, Atonio Miele
In DATE 2016, Design Automation & Test in Europe, Dresden, Germany, March 14-18, 2016, pp. 1 - 6 (*)
2015
A Configurable Board-level Adaptive Incremental Diagnosis Technique based on Decision Trees
Cristiana Bolchini and Luca Cassano
In DFT 2015 the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, University of Massachusetts Amherst, USA, October 12-14, 2015
2014
Using Stochastic Activity Networks to Study the Energy Feasibility of Automatic Weather Stations
Luca Cassano, Daniel Cesarini, Marco Avvenuti
In MSCSE 2014 the Symposium on Modelling and Simulation in Computer Sciences and Engineering, Rhodes, Greece, September 22-28, 2014
Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems
Domenico Sorrenti, Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Mario Porrmann and Cinzia Bernardeschi
In DFT 2014 the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, The Netherlands, October 1-3, 2014
Machine Learning-based Techniques for Board-level Incremental Functional Diagnosis: a Comparative Analysis
Cristiana Bolchini and Luca Cassano
In DFT 2014 the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, The Netherlands, October 1-3, 2014 (*)
Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
Luca Cassano, C. Bernardeschi, A. Domenici
In ITC 2014 the International Test Conference, Seattle, Washington, USA, October 21-23, 2014
Early Assessment of SEU Sensitivity through Untestable Faults Identification
Luca Cassano, Hipolito Guzman-Miranda and Miguel Angel Aguirre
In IOLTS 2014 the 20th IEEE International On-Line Testing Symposium, Platja d'Aro, Catalunya, Spain, July 7-9, 2014
An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems
Luca Cassano, Dario Cozzi, Dirk Jungewelter, Sebastian Korf, Jens Hagemeyer, Mario Porrmann and Cinzia Bernardeschi
In DTIS 2014 the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era,
Santorini, Greece, May 6-8, 2014
A novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMR
Luca Cassano, Alberto Bosio and Giorgio Di Natale
In ETS 2014 the 19th IEEE European Test Symposium,
Paderborn, Germany, May 26-30, 2014
Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations
Daniel Cesarini, Luca Cassano, Alessio Fagioli and Marco Avvenuti
In ES4CPS 2014 the DATE 2014 Workshop on Engineering Simulations for Cyber-Physical Systems,
Bremen, Germany, March 28, 2014
2013
Mitigation of Single Event Upsets in the Control Logic of a Charge Equalizer for Li-ion Batteries
Federico Baronti, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Roberto Roncella, Roberto Saletti
In IECON 2013 the 39th Annual Conference of the IEEE Industrial Electronics Society,
Vienna, Austria, November 10-13, 2013 (*)
Simulation of Automatic Weather Stations for the Energy Estimation of Sensing and Communication Software Policies
Marco Avvenuti, Luca Cassano, Daniel Cesarini and Silvia Mandalá
In ExtremeCom 2013, The 5th Extreme Conference on Communication,
Iceland, August 24-30, 2013 (*)
Formal approaches to SEU testing in FPGAs
Cinzia Bernardeschi, Luca Cassano and Andrea Domenici
In AHS 2013, The NASA/ESA Conference on Adaptive Hardware and Systems,
Torino, Italy, June 25-27, 2013 (*)
Unexcitability Analysis of SEUs Affecting the Routing Structure of SRAM-based FPGAs
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici and Luca Sterpone
In GLSVLSI 2013, The 23rd Great Lakes Symposium on Very Large Scale of Integration,
Paris, France, May 2-3, 2013 (*)
On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems
Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann and Luca Sterpone
In DATE 2013, Design Automation & Test in Europe,
Grenoble, France, March 18-22, 2013
2012
Accurate Simulation of SEUs in the Configuration Memory of SRAM-based FPGAs
Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone
In DFT 2012, The 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems,
Austin, Texas, USA, October 3-5, 2012 (*)
SEU-X: a SEu Un-eXcitability prover for SRAM-FPGAs
C. Bernardeschi, L. Cassano, A. Domenici
In IOLTS 2012, The 18th IEEE International On-Line Testing Symposium,
Sitges, Spain, June 27-29, 2012 (*)
2011
Simulated Injection of Radiation-Induced Logic Faults in FPGAs
C. Bernardeschi, L. Cassano, A. Domenici, G. Gennaro, M. Pasquariello
In VALID 2011, The Third International Conference on Advances in System Testing and Validation Lifecycle,
Barcelona, Spain, October 23-28, 2011 (*)
A Tool for Signal Probability Analysis of FPGA-Based Systems (Winner of the best paper award)
C. Bernardeschi, L. Cassano, A. Domenici, P. Masci
In COMPUTATION TOOLS 2011, The Second International Conference on Computational Logics, Algebras, Programming, Tools, and Benchmarking,
Rome, Italy, September 25-30, 2011 (*)
Failure Probability and Fault Observability of SRAM-FPGA Systems
C. Bernardeschi, L. Cassano, A. Domenici
In FPL 2011, the 21st International Conference on Field Programmable Logic and Applications,
Chania, Crete, Greece, September 5-7, 2011 (*)
Failure Probability of SRAM-FPGA Systems with Stochastic Activity Networks
C. Bernardeschi, L. Cassano, A. Domenici
In DDECS 2011, the 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems,
Cottbus, Germany, April 13-15, 2011 (*)[pdf] [bibtex]
2010
Debugging PVS Specifications of Control Logics via Event-driven Simulation (Winner of the best paper award)
C. Bernardeschi, L. Cassano, A. Domenici, P. Masci
In COMPUTATION TOOLS 2010, the First International Conference on Computational Logics, Algebras, Programming, Tools, and Benchmarking,
Lisbon, Portugal, November 21-26, 2010. (*)[pdf] [bibtex]
Other Talks
2021
DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN
Luca Cassano, Mattia Iamundo, Tomas Antonio Lopez, Alessandro Nazzari, Giorgio Di Natale
In ITASEC 2021 the Italian Conference on Cybersecurity, Online, April 7-9, 2021 (*)
2014
Reducing the Effort for Board-level Functional Diagnosis through Incremental Test Execution
Cristiana Bolchini, Luca Cassano
In ITC 2014 the International Test Conference, Seattle, Washington, USA, October 21-23, 2014 (*)
Multi-stage Cross-layer Hardware Trojan Prevention, Detection and Tolerance
Cristiana Bolchini, Luca Cassano, Giorgio Di Natale
In the Joint MEDIAN-TRUDEVICE Open Forum, Amsterdam, The Netherlands, September 30, 2014 (*)
Detecting Possible Locations for Hardware Trojans by Identifying Untestable Faults
Cristiana Bolchini and Luca Cassano
In TRUDEVICE 2014 the 2nd Workshop on Test and Fault Tolerance for Secure Devices, Paderborn, Germany, May 29-30, 2014 (*)
Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
Luca Cassano
In the 2014 E.J. McCluskey Doctoral Thesis Award Semifinals Located at ETS 2014,
Paderborn, Germany, May 26-30, 2014
Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
Luca Cassano
In the EDAA/ACM SIGDA PhD Forum at DATE 2014,
Bremen, Germany, March 24-28, 2014
2013
A CAD Flow for On-Line Testing and Patching Permanent Radiation Effects in Reconfigurable Systems
Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann and Luca Sterpone
In the SEE/MAPLD 2013 joint session of the Single Event Effects Symposium and Military and Aerospace Programmable Logic Devices Conference,
San Diego, California, USA, April 9-12, 2013
2012
A CAD Flow for the Analysis of the Sensitivity to SEUs of SRAM-FPGAs
Luca Cassano
In SEFUW 2012, The 1st ESA SpacE FPGA Users Workshop,
Nordwjik, The Netherlands, November 6-7, 2012
Application of a Genetic Algorithm for Testing SEUs in SRAM-FPGA Systems
C. Bernardeschi, L. Cassano, M.G.C.A. Cimino, A. Domenici
In WRC 2012, The 6th HiPEAC Workshop on Reconfigurable Computing,
Paris, France, January 24, 2012 (*)
Invited talks and seminars
2022
Advanced Topics in HW Security
Luca Cassano
At the Departamento de Ingeniería Telemática de la Universidad Carlos III de Madrid, December 19, 2022
2020
Reliability Analysis and Design for ML-based Applications
Cristiana Bolchini, Luca Cassano, Antonio Miele
At Agenzia Spaziale Italiana, Rome, Italy, February 13, 2020
(*)
Fault Tolerant and Secure Embedded Systems
Luca Cassano
At the Department of Electronic Engineering of the University of Rome Tor Vergata, January 31, 2020
2013
Analysis and Test of the Effects of Single Event Upsets in the Configuration Memory of SRAM-based FPGA Systems
Luca Cassano
At Istituto di Scienza e Tecnologie dellInformazione A. Faedo - National Research Council of Italy (CNR), Pisa, Italy, March 1, 2013
2012
Reconfigurable Systems: the Dynamically Reconfigurable Processing Module Project
Luca Cassano
At Department of Information Engineering, University of Pisa, Italy, October 22, 2012
Tools for the Analysis of SEU Effects into SRAM-FPGA Systems
Luca Cassano
At Cluster of Excellence Center in Cognitive Interactive Technology (CITEC) - University of Bielefeld, Germany, April 20, 2012
An Introduction to Fault Detection in FPGA Systems
Luca Cassano
At Department of Information Engineering, University of Pisa, Italy, January 31, 2012
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