Luca Cassano, Ph.D.
Associate Professor

Department of Electronics, Informatics and Bioengineering
Politecnico di Milano
via Ponzio 34/5, 20133, Milano, Italy
tel.: +39-02-23994174

I am an associate professor at the Department of Electronics, Informatics and Bioengineering, Politecnico di Milano, Italy.

I received my Bachelor's degree and my Master's degree in Computer Engineering in 2006 and 2009 respectively from the University of Pisa, Italy. In 2013 I received my Ph.D. in Information Engineering from the Department of Information Engineering of the University of Pisa. From March 2013 until June 2013 I have been a post doctoral research fellow at Istituto di Scienza e Tecnologie dell'Informazione "A. Faedo", National Research Council. From July 2013 until January 2016 I have been a post doctoral research fellow at the Dipartimento di Elettronica, Informazione e Bioingegneria of the Politecnico di Milano, Italy. Finally, from February 2017 until September 2017 I worked as an Associate Memebr of the Technical Staff at Maxim Integrated. During my Ph.D. course I spent a visiting period at the Department of Automation and Informatics of the Politecnico di Torino, Italy, and a visiting period at the Cognitive Interaction Technology - Center of Excellence (CITEC) of the University of Bielefeld, Germany.

With my Ph.D. thesis, titled "Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs", I won the European semi-finals of the TTTC's E. J. McCluskey Doctoral Thesis Award held during ETS2014, in Paderborn, Germany, on May 26-30 2014, and I was the runner-up at the Award finals held during ITC2014, in Seattle, USA, on November 21-23 2014.

Here you can find my CV.
Research activity:

My research interests are:

1) Reliability Analysis and Hardening of Deep Learning Application (CNNs, RNNs...)
2) Hardware Security, mainly focusing on Hardware Trojan Horses and Microarchitectural Side-Channel Attacks (Spectre, Meltdown...)
3) Analysis of Reliability and Security properties of RISC-V microprocessors
4) Fault Simulation, Automatic Test Pattern Generation, Testability Analysis and Fault Diagnosis for digital circuits and systems
5) Design of Fault Tolerant digital circuits and systems


Master Thesis Proposals

Teaching activity:

Fondamenti di Informatica

Design of HW Accelerators