Luca Cassano, Ph.D.
Assistant Professor

Department of Electronics, Informatics and Bioengineering
Politecnico di Milano
via Ponzio 34/5, 20133, Milano, Italy
tel.: +39-02-23994174;
e-mail: luca.cassano@polimi.it


I am an assistant professor at the Department of Electronics, Informatics and Bioengineering, Politecnico di Milano, Italy.

I received my Bachelor's degree and my Master's degree in Computer Engineering in 2006 and 2009 respectively from the University of Pisa, Italy. In 2013 I received my Ph.D. in Information Engineering from the Department of Information Engineering of the University of Pisa.
From March 2013 until June 2013 I have been a post doctoral research fellow at Istituto di Scienza e Tecnologie dell'Informazione "A. Faedo", National Research Council, under the supervision of Doctor Stefania Gnesi. From July 2013 until January 2016 I have been a post doctoral research fellow at the Dipartimento di Elettronica, Informazione e Bioingegneria of the Politecnico di Milano, Italy, under the supervision of Professor Cristiana Bolchini. Finally, from February 2017 until September 2017 I worked as an Associate Memebr of the Technical Staff at Maxim Integrated.
During my Ph.D. course I spent a visiting period at the Department of Automation and Informatics of the Politecnico di Torino, Italy, under the supervision of Doctor Luca Sterpone, and a visiting period at the Cognitive Interaction Technology - Center of Excellence (CITEC) of the University of Bielefeld, Germany, under the supervision of Professor Mario Porrmann.

With my Ph.D. thesis, titled "Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs", I won the European semi-finals of the TTTC's E. J. McCluskey Doctoral Thesis Award held during ETS2014, in Paderborn, Germany, on May 26-30 2014, and I was the runner-up at the Award finals held during ITC2014, in Seattle, USA, on November 21-23 2014.

Here you can find my CV.
Research activity:

My research interests are:

1) Analysis of the effects of SEUs in the configuration memory of SRAM-based FPGA systems.
2) Fault Simulation, Automatic Test Pattern Generation and fault untestability analysis for digital circuits and systems.
3) Use of machine learning and data mining techniques for fault testing and diagnosis for digital circuits and systems.
4) Energy-aware modeling and simulation of Automatic Weather Station.
5) Use of formal and semi-formal methods for dynamic system modelling and analysis (functional verification, safety analysis...)

Publications

Professional activity:

Here you can find the list of my editorial activities.

Teaching activity:

Informatica B (In Italian)