Rescuer Logo RESCUER: The first workshop on REliable and SeCUrE RISC-V architectures
29-30 May, 2025, Tallinn, Estonia

Workshop Program

Thursday, May 29th, 2025
16:30 – 16:40
Opening
Luca Cassano (Politecnico di Milano, IT)
Gianluca Furano (European Space Agency, NL)
16:40 – 17:30
Keynote 1
Dependable computing with Silicon Lifecycle Management
Jyotika Athavale (Synopsys, USA)
17:30 – 18:30
Keynote 2
Closing holes with open architecture
Andrew Dellow (Qualcomm, UK)
18:30
Welcome Cocktail
Friday, May 30th, 2025
09:00 – 10:00
Keynote 3
From SPARC to RISC-V: Architecting Intelligent and Dependable Processors for Space Applications
Gianluca Furano (European Space Agency, NL)
10:00 – 10:30
Coffee Break
10:30 – 11:15
Technical Session 1
Characterization of HARV-SoC for Reliable Avionics Applications
Wesley GRIGNANI1, Douglas SANTOS1, Carolina IMIANOSKY1, Maria KASTRIOTOU2, Cazzaniga CARLO2, Luigi DILILLO1
1IES, University of Montpellier, CNRS, Montpellier, FR; 2ISIS Facility, STFC, Rutherford Appleton Laboratory, Oxfordshire, UK
Klessydra-f: The Fault Tolerant Family of RISC-V Interleaved Multi-Threading Processors
Andrea MARCELLI, Marcello BARBIROTTA, Marco ANGIOLI, Antonio MASTRANDREA, Francesco MENICHELLI, Abdallah CHEIKH, Mauro OLIVIERI
Dept. of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, IT
11:15 – 12:00
Technical Session 2
Investigating Undervolting Effects on RISC-V Implemented in FPGA
Ioanna SOUVATZOGLOU, Konstantinos ARGYRIOU, Grigorios KARAOGLANIAN, Dimitrios AGIAKATSIKAS, Mihalis PSARAKIS
Department of Informatics, University of Piraeus, GR
Computing Failure Rates by Examining ECC Errors Under Accelerated Radiation Beam
Tijmen T. SMIT1, Elijah CISHUGI1, Bruno ENDRES FORLIN1, Kuan-Hsun CHEN1, Marco OTTAVI1,2
1University of Twente, NL; 2University of Rome Tor Vergata, IT
12:00 – 13:30
Lunch
13:30 – 14:30
Technical Session 3
Evaluating the Vulnerabilities of TETRISC SoC Under Laser Fault Injection
Junchao CHEN1, Dmytro PETRYK1, Markus ULBRICHT1, Milos KRSTIC1,2
1IHP - Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), DE; 2University of Potsdam, Potsdam, DE
RISC-V Processors Evaluation: Benchmarking Performance, Power Consumption, Area, and Security
Elia LAZZERI1, Gianluca FURANO2, Luca CASSANO1
1Politecnico di Milano, IT; 2European Space Agency, NL
Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide
Behnam FARNAGHINEJAD, Antonio PORSIA, Annachiara RUOSPO, Alessandro SAVINO, Stefano DI CARLO, ERNESTO SANCHEZ
Department of Control and Computer Engineering, Politecnico di Torino, Turin, IT
14:30 – 15:10
Technical Session 4
SECUR-V: A Framework for Security and Verification of RISC-V Against Architectural Attacks and Hardware Trojans
Tara GHASEMPOURI1, Giorgio DI NATALE2
1Tallinn University of Technology, EE; 2Univ. Grenoble Alpes, CNRS, Grenoble INP*, TIMA, FR
A Benchmark Suite of Transient Execution Attacks for RISC-V Processors
Elia LAZZERI1, Gianluca FURANO2, Luca CASSANO1
1Politecnico di Milano, IT; 2European Space Agency, NL
15:10 – 15:15
Closing Session
15:15 – 15:30
Coffee Break